论文标题
使用BCH代码的多项式基础，在多项式基础上，位平行乘数的有效故障检测结构
Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code
论文作者
论文摘要
有限的字段乘数主要用于当今许多最先进的数字系统，其用于位并行操作的硬件实现可能需要数百万个逻辑门。数字设计中的自然原因或软错误可能会导致其中一些大门在现场发生故障，从而导致乘数产生不正确的输出。为了确保它们不易出现错误，使用有效且具有高故障检测能力的有限场乘数实现至关重要。在本文中，我们提出了一种新型的故障检测方案，用于与GF（2M）上最近的比特平行多项式乘数（2M），其中所提出的方法旨在获得有限场乘数的高故障检测性能，同时保持低复杂性实现，这在资源约束中受到诸如智能卡等资源约束的青睐。所提出的方法基于BCH误差校正代码，并具有区域延迟有效体系结构。实验结果表明，与[18]中现有方法相比，对于5位误差的45位乘数和5位误差所提出的误差检测和校正结构的临界路径延迟减少了37％，而校正结构则减少了。此外，有5个错误的45位乘数的开销范围在80％以内，这显着低于有限字段乘数中基于BCH的最佳故障检测方法[18]。
The finite field multiplier is mainly used in many of today's state of the art digital systems and its hardware implementation for bit parallel operation may require millions of logic gates. Natural causes or soft errors in digital design could cause some of these gates to malfunction in the field, which could cause the multiplier to produce incorrect outputs. To ensure that they are not susceptible to error, it is crucial to use a finite field multiplier implementation that is effective and has a high fault detection capability. In this paper, we propose a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), where the proposed method aims at obtaining high fault detection performance for finite field multipliers and meanwhile maintain low-complexity implementation which is favored in resource constrained applications such as smart cards. The proposed method is based on BCH error correction codes, with an area-delay efficient architecture. The experimental results show that for 45-bit multiplier with 5-bit errors the proposed error detection and correction architecture results in 37% and %49 reduction in critical path delay with compared to the existing method in [18]. Moreover, the area overhead for 45-bit multiplier with 5 errors is within 80% which is significantly lower than the best existing BCH based fault detection method in finite field multiplier [18].
