论文标题

比最坏情况的解码更好

Better Than Worst-Case Decoding for Quantum Error Correction

论文作者

Ravi, Gokul Subramanian, Baker, Jonathan M., Fayyazi, Arash, Lin, Sophia Fuhui, Javadi-Abhari, Ali, Pedram, Massoud, Chong, Frederic T.

论文摘要

超导量子系统上的量子误差校正的经典解码的开销迅速随逻辑Qubits的数量及其校正代码距离而迅速增长。室温下的解码是由冰箱I/O带宽瓶瓶,而芯片芯片解码受面积/功率/热预算的限制。 为了克服这些间接费用,我们的动机是,在常见的情况下,误差签名是相当微不足道的,具有高冗余/稀疏性,因为误差校正代码过多以纠正不常见的最常见的案例复杂场景(以确保实质上低逻辑错误率实质性低))。如果适当利用,这些微不足道的签名可以用微不足道的开销来解码和纠正,从而减轻上述瓶颈,同时仍通过最终的手段处理最坏的案例复杂签名。 我们的建议,针对地面代码,包括: 1)集团:用于解码和纠正琐碎的普通案例误差的轻量级解码器,该错误是为低温域而设计的。该解码器是针对SFQ逻辑实现的。 2)一种基于统计置信的技术,用于芯片解码带宽分配,以有效处理片上解码器未涵盖的稀有复合解码。 3)一种停滞电路执行的方法,对于最糟糕的场景,在该场景中,配置后的离子带宽不足以完成所有请求的芯片外解。 总的来说,我们的建议可以在一系列逻辑和物理错误率上消除70-99+%的离芯片带宽消除,而无需显着牺牲最先进的外芯片外解码的准确性。通过这样做,它可以比先前的离子外带宽减少技术实现10-10000x带宽减少。此外,与先前的仅芯片解码相比,它可实现15-37倍的资源间接费用。

The overheads of classical decoding for quantum error correction on superconducting quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottle-necked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case, error signatures are fairly trivial with high redundancy/sparsity, since the error correction codes are over-provisioned to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial signatures can be decoded and corrected with insignificant overhead, thereby alleviating the bottlenecks described above, while still handling the worst-case complex signatures by state-of-the-art means. Our proposal, targeting Surface Codes, consists of: 1) Clique: A lightweight decoder for decoding and correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented for SFQ logic. 2) A statistical confidence-based technique for off-chip decoding bandwidth allocation, to efficiently handle rare complex decodes which are not covered by the on-chip decoder. 3) A method for stalling circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, our proposal enables 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of state-of-the-art off-chip decoding. By doing so, it achieves 10-10000x bandwidth reduction over prior off-chip bandwidth reduction techniques. Furthermore, it achieves a 15-37x resource overhead reduction compared to prior on-chip-only decoding.

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