论文标题
通用地址序列生成器，用于内置自我测试
Universal Address Sequence Generator for Memory Built-in Self-test
论文作者
论文摘要
本文介绍了通用地址序列发生器（UASG），用于内置内置测试。这些研究基于提出的通用方法，该方法用于生成具有多室March记忆测试所需属性的地址序列。作为数学模型，使用了准随机序列产生的递归关系的修改。对于此模型，给出了硬件实现的结构图，其基础是存储生成矩阵的所谓方向数的存储设备。生成矩阵的形式确定生成的地址序列的基本属性。所提出的UASG生成了各种不同的地址序列，包括标准序列，例如线性，地址补充，灰色代码，最差的门延迟，$ 2^i $，下一个地址和伪andom。考虑了使用建议方法的示例。提出了UASG实际实施的结果，并评估了主要特征。
This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, $2^i$, next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.
