论文标题
开发TRL5空间合格的硬件,用于调整,偏置和读取kilopixel TES Bologe阵列
Development of TRL5 Space Qualified Hardware for Tuning, Biasing, and Readout of Kilopixel TES Bolometer Arrays
论文作者
论文摘要
下一代基于太空的MM波望远镜(例如Jaxa的Litebird Mission)需要焦点飞机,以实现数千个检测器,以实现其科学目标。数字频域多路复用(DFMUX)技术使探测器计数可以扩展,而无需线性施用线性生长,子凯文氏冰箱负载和其他缩放问题。在本文中,我们介绍了技术准备级别5(TRL5)电子设备,适用于使用DFMUX技术偏置和读数LiteBird的过渡边缘传感器(TES)强仪。这些电子设备位于航天器的有效载荷计算机和低温焦平面之间,并在这些探测器和航天器的板载存储之间提供探测器的偏置,调谐和读数接口。我们描述了电子设备的整体体系结构,包括功能分解为模块,这些模块的命理和互连及其内部和外部接口。我们描述迄今为止的性能测量,包括功耗,热性能以及质量,体积和可靠性估算值。本文是对电子机上现场可编程门阵列(FPGA)固件的描述的伴侣作品。
The next generation of space-based mm-wave telescopes, such as JAXA's LiteBIRD mission, require focal planes with thousands of detectors in order to achieve their science goals. Digital frequency-domain multiplexing (dfmux) techniques allow detector counts to scale without a linear growth in wire harnessing, sub-Kelvin refrigerator loads, and other scaling problems. In this paper, we introduce Technology Readiness Level 5 (TRL5) electronics suitable for biasing and readout of LiteBIRD's Transition Edge Sensor (TES) bolometers using dfmux techniques. These electronics sit between the spacecraft's payload computer and the cryogenic focal plane, and provide detector biasing, tuning, and readout interfaces between these detectors and the spacecraft's on-board storage. We describe the overall architecture of the electronics, including functional decomposition into modules, the numerology and interconnection of these modules, and their internal and external interfaces. We describe performance measurements to date, including power consumption, thermal performance, and mass, volume, and reliability estimates. This paper is a companion piece to a description of the electronics' on-board Field-Programmable Gate Array (FPGA) firmware.