论文标题
基于硬件的HEFT调度程序实现，用于异质SOC的动态工作负载
A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs
论文作者
论文摘要
与同质体系结构相比，异质SOC的整个加工元素（PE）的不均匀性能和功耗增加了任务调度问题的计算复杂性。基于软件的调度程序在PES数量和类型方面具有提高异质性水平的延迟，这是有必要将调度程序部署为硬件中的覆盖处理器，以便能够快速地做出调度决策，并能够在异构SOC上部署现实生活应用程序。在这项研究中，我们介绍了在FPGA上实施和部署最早的最早完成时间算法（HEFT_RT）的运行时涉及的设计权衡。我们对Xilinx Zynq ZCU102平台模拟的SOC配置进行了性能评估。在运行时环境中，我们演示了基于硬件的HEFT_RT能够平均使用9.144 NS延迟做出调度决策的能力，与其软件对应物相比，每秒的任务增加了26.7％，并根据动态到达现实信号真实信号处理的工作量组成的工作负载，将计划延迟降低至183X的倍数。
Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based scheduler with the increased heterogeneity level in terms of number and types of PEs creates the necessity of deploying a scheduler as an overlay processor in hardware to be able to make scheduling decisions rapidly and enable deployment of real-life applications on heterogeneous SoCs. In this study we present the design trade-offs involved for implementing and deploying the runtime variant of the heterogeneous earliest finish time algorithm (HEFT_RT) on the FPGA. We conduct performance evaluations on a SoC configuration emulated over the Xilinx Zynq ZCU102 platform. In a runtime environment we demonstrate hardware-based HEFT_RT's ability to make scheduling decisions with 9.144 ns latency on average, process 26.7% more tasks per second compared to its software counterpart, and reduce the scheduling latency by up to a factor of 183x based on workloads composed of mixture of dynamically arriving real-life signal processing applications.
