论文标题
了解降低的文字线电压下的行锤：使用真实DRAM设备的实验研究
Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices
论文作者
论文摘要
Rowhammer是电路级的DRAM漏洞，在该漏洞中反复激活和预处理一排dram行，因此在低压和高电压级别之间交替了一行文字线的电压，可能会导致物理上附近的行中的钻头翻转。最近的DRAM芯片更容易受到Rowhammer的攻击：随着技术节点缩放，激活式式循环的最小数量以诱导Rowhammer位flip降低，而Rowhammer位错误率也会增加。因此，开发有效且可扩展的方法以保护现代DRAM系统免受Rowhammer的影响至关重要。为了实现此类解决方案，必须深入了解现代DRAM芯片的Rowhammer脆弱性。但是，即使在文字线上切换的电压是Rowhammer漏洞的关键决定因素，但没有事先的工作在实验上证明Wordline电压（VPP）对Rowhammer漏洞的影响。我们的工作缩小了理解差距。 这是在272个真实的DRAM芯片上进行实验证明的第一项工作，该芯片降低了VPP可减少DRAM芯片的Rowhammer脆弱性。我们表明，降低VPP 1）将诱导Rowhammer Bit Flip的激活式循环数量增加高达85.8％，所有测试芯片的平均为7.4％，而2）将Rowhammer位误差率降低66.9％，在所有测试过的芯片中平均为15.2％。同时，减少VPP的略微使DRAM单元的访问延迟，充电恢复和数据保留时间在系统级标称定时参数的护罩中，其中208个272个经过测试的芯片中的208个。我们得出的结论是，减少VPP是减少DRAM芯片的Rowhammer脆弱性而无需修改DRAM芯片的有前途的策略。
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and precharging a DRAM row, and thus alternating the voltage of a row's wordline between low and high voltage levels, can cause bit flips in physically nearby rows. Recent DRAM chips are more vulnerable to RowHammer: with technology node scaling, the minimum number of activate-precharge cycles to induce a RowHammer bit flip reduces and the RowHammer bit error rate increases. Therefore, it is critical to develop effective and scalable approaches to protect modern DRAM systems against RowHammer. To enable such solutions, it is essential to develop a deeper understanding of the RowHammer vulnerability of modern DRAM chips. However, even though the voltage toggling on a wordline is a key determinant of RowHammer vulnerability, no prior work experimentally demonstrates the effect of wordline voltage (VPP) on the RowHammer vulnerability. Our work closes this gap in understanding. This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability. We show that lowering VPP 1) increases the number of activate-precharge cycles needed to induce a RowHammer bit flip by up to 85.8% with an average of 7.4% across all tested chips and 2) decreases the RowHammer bit error rate by up to 66.9% with an average of 15.2% across all tested chips. At the same time, reducing VPP marginally worsens a DRAM cell's access latency, charge restoration, and data retention time within the guardbands of system-level nominal timing parameters for 208 out of 272 tested chips. We conclude that reducing VPP is a promising strategy for reducing a DRAM chip's RowHammer vulnerability without requiring modifications to DRAM chips.
