论文标题
设计和实施安全的RISC-V微处理器
Design and Implementation of a Secure RISC-V Microprocessor
论文作者
论文摘要
可以从未受保护的设备的功耗或电磁发射中提取秘密密钥。传统的反措施的保护范围有限，并且对必须如何操纵敏感数据施加了一些限制。我们演示了没有普通文本数据的小串行RISC-V微处理器实现。所有值均使用布尔屏蔽保护。软件几乎可以运行，几乎没有相反测量，减少代码大小和性能开销。与以前的文献不同，我们的方法是完全自动化的，可以应用于任意大小或复杂性的设计。我们还提供有关其他关键组件的详细信息，例如时钟随机器，内存保护和随机数生成器。微处理器是在65 nm CMOS技术中实施的。使用NIST测试以及侧渠道攻击对其实施进行了评估。我们的RNG通过所有NIST测试生成的随机数。基线实现的侧通道分析仅使用375个轨迹提取了AES密钥，而我们的安全微处理器能够使用20 M痕迹来承受攻击。
Secret keys can be extracted from the power consumption or electromagnetic emanations of unprotected devices. Traditional counter-measures have limited scope of protection, and impose several restrictions on how sensitive data must be manipulated. We demonstrate a bit-serial RISC-V microprocessor implementation with no plain-text data. All values are protected using Boolean masking. Software can run with little to no counter-measures, reducing code size and performance overheads. Unlike previous literature, our methodology is fully automated and can be applied to designs of arbitrary size or complexity. We also provide details on other key components such as clock randomizer, memory protection, and random number generator. The microprocessor was implemented in 65 nm CMOS technology. Its implementation was evaluated using NIST tests as well as side channel attacks. Random numbers generated with our RNG pass on all NIST tests. Side-channel analysis on the baseline implementation extracted the AES key using only 375 traces, while our secure microprocessor was able to withstand attacks using 20 M traces.
