论文标题
一种新型的ASIC设计流，使用重量可调的二进制神经元作为标准细胞
A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells
论文作者
论文摘要
在本文中，我们描述了二进制神经元（又称感知器，阈值逻辑门）的混合信号电路的设计和一种自动嵌入此类细胞ASIC的方法。二进制神经元称为FTL（闪光阈值逻辑）使用浮动门或闪光晶体管，其阈值电压是神经元重量的代理。提出了用于将重量映射到闪光晶体管阈值电压的算法。确定阈值电压以最大程度地提高细胞的鲁棒性及其速度。与常规的CMOS逻辑当量相比，单个FTL单元的性能，功率和面积被显示出明显较小（79.4％），消耗较少的功率（61.6％），并且运行速度更快（40.3％）。还包括用于编程FTL闪存设备的体系结构和算法。 FTL单元格是标准单元的，旨在允许商业合成和P＆R工具自动将其用于ASIC的合成。通过自动嵌入FTL细胞，在几个ASIC基准上证明了面积和动力无牺牲性能的大量降低。该论文还展示了如何使用FTL细胞来固定制造后的时序误差。
In this paper, we describe a design of a mixed signal circuit for a binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication.
