论文标题
一种硬件软件共同设计方法，可最大程度地减少多核神经形态处理器中的内存资源的使用
A hardware-software co-design approach to minimize the use of memory resources in multi-core neuromorphic processors
论文作者
论文摘要
在电子和生物学中，神经网络的物理实现都具有严重的能量和记忆约束。我们提出了一种硬件软件共同设计方法，用于通过从生物神经网络中汲取灵感来最大程度地减少多核神经形态处理器中的内存资源的使用。我们使用这种方法设计针对小世界网络优化的新路由方案，并为设计新型应用程序特定的多核神经形态芯片提供指南。从提出的层次路由方案开始，我们提出了一种硬件感知的位置算法，该算法优化了为任意网络模型的资源分配。我们使用规范的小世界网络验证算法，并为从其衍生的其他网络提供初步结果。
Both in electronics and biology, physical implementations of neural networks have severe energy and memory constraints. We propose a hardware-software co-design approach for minimizing the use of memory resources in multi-core neuromorphic processors, by taking inspiration from biological neural networks. We use this approach to design new routing schemes optimized for small-world networks and to provide guidelines for designing novel application-specific multi-core neuromorphic chips. Starting from the hierarchical routing scheme proposed, we present a hardware-aware placement algorithm that optimizes the allocation of resources for arbitrary network models. We validate the algorithm with a canonical small-world network and present preliminary results for other networks derived from it.
