论文标题
可测试阵列乘数，以更好地利用C检测性
Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity
论文作者
论文摘要
本文介绍了用于测试（DFT）架构的设计，以快速，可扩展的阵列乘数（MULT）测试。不管多尺寸，我们提出的可测试体系结构，没有原始体系结构的重大更改，都只需要五个测试向量。测试模式产生（TPG）是通过结合C检测性，射击性和确定性TPG方法来完成的。实验结果表明，单个卡住断层的100％故障覆盖率。提出的方法需要少量可检验性硬件插入乘数，对于64位乘数，额外的延迟和面积小于0.5％。
This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture, without major changes in the original architecture, requires only five test vectors. Test pattern generation (TPG) is done by combining C-testability, bijectivity and deterministic TPG methods. Experimental results show 100% fault coverage for single stuck-at faults. The proposed method requires minor testability hardware insertion into the multiplier with extra delay and area overhead of less than 0.5% for a 64-bit multiplier.
