论文标题
在异性FPGA上部分可重构设计的自动平面图
Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs
论文作者
论文摘要
为均匀的FPGA进行了广泛的探索平面图问题。大多数现代的FPGA由可配置逻辑块，DSP块，BRAM等形式的异质资源组成。对于异质FPGA，几乎没有工作。此外，诸如部分可重构性之类的功能允许对可执行设计的正式更改，从而可以增强性能并非常有效地利用资源。在本文中，我们为FPGA中的部分可重构（PR）设计设计了一个平面图，该设计巧妙地决定了三种提议的资源分配方案之一，用于平面图特定类型的可重构区域。我们还提出了一种白空间检测算法，以有效地管理FPGA内部空间，以减少区域和电线长度。 Xilinx Virtex 5和Artix 7 FPGA体系结构上展示了平面图，并且可以轻松地与现有的供应商供应商的位置和路线工具集成在一起。平面图的主要目的是减少电线长度，最大程度地减少浪费的资源和区域。使用MCNC基准评估了我们的平面图的性能。我们将我们提出的平面植物与文献报道的其他先前发表的结果进行了比较。我们观察到整个电线长度以及执行时间都有很大的改善。此外，将平面纸与供应商提供的位置和路线工具（Xilinx Vivado）集成在一起，以自动化地板平面。自动化过程已在图像处理应用程序中使用的部分可重构中值过滤器上进行了测试。
Floorplanning problem has been extensively explored for homogeneous FPGAs. Most modern FPGAs consist of heterogeneous resources in the form of configurable logic blocks, DSP blocks, BRAMs and more. Very little work has been done for heterogeneous FPGAs. In addition, features like partial reconfigurability allow on-the-fly changes to the executable design that can result in enhanced performance and very efficient utilization of resources. In this paper, we have designed a floorplanner for Partially Reconfigurable (PR) designs in FPGA that smartly decides one of the three proposed resource allocation schemes to floorplan a particular type of reconfigurable region. We also propose a White Space Detection algorithm for efficient management of white space inside an FPGA in order to reduce the area and the wire length. The floorplanner is demonstrated on Xilinx Virtex 5 and Artix 7 FPGA architectures and can be easily integrated with existing vendor-supplied Place and Route tools. The main objective of the floorplanner is to reduce the wire length, minimize wasted resources and the area. The performance of our floorplanner is evaluated using MCNC benchmarks. We have compared our proposed floorplanner with other previously published results reported in the literature. We observe a substantial improvement in the overall wire length as well as the execution time. Also, the floorplanner was integrated with vendor supplied place and route tools (Xilinx Vivado) to automate the floorplanning flow. The automation process was tested on a partially reconfigurable median filter used in image processing applications.
