论文标题
HL-LHC的Atlas Tile Calorimeter Link子板的重新设计
Redesign of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC
论文作者
论文摘要
高光度大型强调对撞机（HL-LHC）的2阶段地图集的升级激励了Atlas Tile Calorimeter（Tilecal）读出链路和控制板（女板）的渐进式重新设计。子板（DB）通过两个4.6 Gbps的下行链路和两对9.6 Gbps上行链路与探视器电子设备进行通信。配置命令和LHC正时通过两个CERN辐射Hard GBTX ASIC接收到下链路，并通过Ultrascale+ FPGA传播到前端。同时，FPGA发送数字化PMT样本的连续高速读数，通过上行链路缓慢控制和监视数据。该设计可将单个失败点最小化，并通过使用双重模式冗余（TMR）（TMR）和FPGA中的Xilinx软误差（SEM）来最大程度地降低对SEU和辐射损害的敏感性，并采用环状冗余检查（CRC）在Uplinks和Forward Orror Correction（Fec）中采用Cyclic Recundancy检查（CRC）的误差（FEC）。我们提出了一个DB的重新设计，该数据带来了增强的时机方案，并通过减轻单个事件锁存（SEL）引起的错误并实施更强大的加电和当前监视方案，从而提高了辐射耐受性。
The Phase-2 ATLAS upgrade for the High Luminosity Large Hadron Collider (HL-LHC) has motivated progressive redesigns of the ATLAS Tile Calorimeter (TileCal) read-out link and control board (Daughterboard). The Daughterboard (DB) communicates with the off-detector electronics via two 4.6 Gbps downlinks and two pairs of 9.6 Gbps uplinks. Configuration commands and LHC timing is received through the downlinks by two CERN radiation hard GBTx ASICs and propagated through Ultrascale+ FPGAs to the front-end. Simultaneously, the FPGAs send continuous high-speed readout of digitized PMT samples, slow control and monitoring data through the uplink. The design minimizes single points of failure and reduces sensitivity to SEUs and radiation damage by employing a double-redundant scheme, using Triple Mode Redundancy (TMR) and Xilinx Soft Error Mitigation (SEM) in the FPGAs, adopting Cyclic Redundancy Check (CRC) error verification in the uplinks and Forward Error Correction (FEC) in the downlinks. We present a DB redesign that brings an enhanced timing scheme, and improved radiation tolerance by mitigating Single Event Latch-up (SEL) induced errors and implementing a more robust power-up and current monitoring scheme.
