论文标题
第四纪加法器的最佳实现
Best implementations of quaternary adders
论文作者
论文摘要
将第四纪1位加法器的实施与二进制解码器的第四纪和二元编码器与二元编码器组成的实施与最近的第四纪加法器的几个实现进行了比较。这种简单的实现仅使用一个电源优于所有其他实现。它等同于使用三个电源的最好的其他实现。与二进制加法器相比，使用2位二进制加法器的最佳四级加法器使用2位二进制加法器，第四纪和二元级别之间的接口电路刚好是头顶的。该结果表明，与相应的二进制文件相比，加成器的第四纪方法使用更多的晶体管，更多的芯片区域和更多的功率耗散。
The implementation of a quaternary 1-digit adder composed of a 2-bit binary adder, quaternary to binary decoders and binary to quaternary encoders is compared with several recent implementations of quaternary adders. This simple implementation outperforms all other implementations using only one power supply. It is equivalent to the best other implementation using three power supplies. The best quaternary adder using a 2-bit binary adder, the interface circuits between quaternary and binary levels are just overhead compared to the binary adder. This result shows that the quaternary approach for adders use more transistors, more chip area and more power dissipation than the corresponding binary ones.
