论文标题

突触重量的后端CMOS兼容铁电场效应晶体管

A back-end, CMOS compatible ferroelectric Field Effect Transistor for synaptic weights

论文作者

Halter, Mattia, Bégon-Lours, Laura, Bragaglia, Valeria, Sousa, Marilyne, Offrein, Bert Jan, Abel, Stefan, Luisier, Mathieu, Fompeyriney, Jean

论文摘要

神经形态计算体系结构使单个电路内的存储器和处理元素的密集共同位置。此共处将消除在单独的内存和计算单元之间传输数据的通信瓶颈,如标准von Neuman架构中的数据关键应用程序,包括机器学习。神经形态系统的基本构件是非易失性的突触元素,例如回忆录。关键的MEMRISTOR性质包括合适的非挥发性电阻范围,连续线性电阻调制和对称切换。在这项工作中,我们演示了电压控制,对称和模拟增强和抑郁症的hf $ _ {57} $ zr $ _ {43} $ o $ $ $ _ {2} $(Hzo)fielder transistor(feFET),并具有良好的线性线性。我们的FEFET以低写作能量(FJ)和快速编程时间(40 ns)运行。保留测量已超过4位深度,在氧化钨(wo $ _ {x} $)中读出通道。通过将通道厚度从15nm调整到8nm,FEFET的ON/OFF比率可以根据频道的几何形状来理想地> 100 KOHM,从而使FEFET的ON/OFT比率从1%到200%进行工程。该设备概念是使用土壤丰富的材料,并且与线的后端(BEOL)集成到互补的金属 - 氧化物指导器(CMOS)过程中。因此,它具有制造高密度的大型集成阵列的人造模拟突触的巨大潜力。

Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are non-volatile synaptic elements such as memristors. Key memristor properties include a suitable non-volatile resistance range, continuous linear resistance modulation and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf$_{57}$Zr$_{43}$O$_{2}$ (HZO) field effect transistor (FeFET) with good linearity. Our FeFET operates with a low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been done over 4-bits depth with low noise (1%) in the tungsten oxide (WO$_{x}$) read out channel. By adjusting the channel thickness from 15nm to 8nm, the on/off ratio of the FeFET can be engineered from 1% to 200% with an on-resistance ideally >100 kOhm, depending on the channel geometry. The device concept is using earth-abundant materials, and is compatible with a back end of line (BEOL) integration into complementary metal-oxidesemiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high density, large-scale integrated arrays of artificial analog synapses.

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